Question
Write a verilog code for synchronous and asynchronous reset?
Answers
Synchronous reset, synchronous means clock dependent so reset must not be present in sensitivity disk
eg: always @ (posedge clk )
begin if (reset). . . end
Asynchronous means clock independent so reset must be present in sensitivity list.
Eg: Always @(posedge clock or posedge reset)
beginif (reset). . . end   Your Comment




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